Invention Grant
- Patent Title: Chip scale package
-
Application No.: US17245259Application Date: 2021-04-30
-
Publication No.: US11562952B2Publication Date: 2023-01-24
- Inventor: Craig McAdam , Jonathan Taylor , Douglas Macfarlane , John Kerr , James Munger , John Pavelka , Steven A. Atherton
- Applicant: Cirrus Logic International Semiconductor Ltd.
- Applicant Address: GB Edinburgh
- Assignee: Cirrus Logic International Semiconductor Ltd.
- Current Assignee: Cirrus Logic International Semiconductor Ltd.
- Current Assignee Address: GB Edinburgh
- Agency: Jackson Walker L.L.P.
- Main IPC: H01L23/498
- IPC: H01L23/498 ; H01L23/00
Abstract:
The present disclosure relates to a chip scale package (CSP) comprising: a first set of CSP contact balls or bumps; a second set of CSP contact balls or bumps; and a channel routing region, the channel routing region being devoid of any CSP contact balls or bumps.
Public/Granted literature
- US20220246514A1 CHIP SCALE PACKAGE Public/Granted day:2022-08-04
Information query
IPC分类:
