Invention Grant
- Patent Title: System and method for scalable hardware-coherent memory nodes
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Application No.: US16944905Application Date: 2020-07-31
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Publication No.: US11586541B2Publication Date: 2023-02-21
- Inventor: Derek Schumacher , Randy Passint , Thomas McGee , Michael Malewicki , Michael S. Woodacre
- Applicant: Hewlett Packard Enterprise Development LP
- Applicant Address: US TX Houston
- Assignee: Hewlett Packard Enterprise Development LP
- Current Assignee: Hewlett Packard Enterprise Development LP
- Current Assignee Address: US TX Houston
- Agency: Park, Vaughan, Fleming & Dowler LLP
- Main IPC: G06F12/08
- IPC: G06F12/08 ; G06F13/40 ; G06F12/0815

Abstract:
One embodiment can provide a node controller in a multiprocessor system. The node controller can include a processor interface to interface with a processor, a memory interface to interface with a fabric-attached memory, a node-controller interface to interface with a remote node controller, and a cache-coherence logic to operate in a first mode or a second mode. The cache-coherence logic manages cache coherence for a local memory of the processor coupled to the processor interface when operating in the first mode, and the cache-coherence logic manages cache coherence for the fabric-attached memory coupled to the memory interface when operating in the second mode.
Public/Granted literature
- US11714755B2 System and method for scalable hardware-coherent memory nodes Public/Granted day:2023-08-01
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