A memory device including a clock generator generating a data processing clock signal based on an external clock signal, and an input/output circuit performing a data transmission/reception operation of transmitting/receiving data to/from an external device based on the data processing clock signal, wherein the clock generator comprises a warm-up operation controller generating a warm-up enable signal for recognizing a portion of a period of the external clock signal as a dummy signal, and resetting the warm-up enable signal when a pause period where a toggle of the external clock signal is temporarily stopped is detected.