- 专利标题: EFuse circuit, method, layout, and structure
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申请号: US17541245申请日: 2021-12-02
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公开(公告)号: US11621046B2公开(公告)日: 2023-04-04
- 发明人: Meng-Sheng Chang , Yao-Jen Yang
- 申请人: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- 申请人地址: TW Hsinchu
- 专利权人: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- 当前专利权人: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- 当前专利权人地址: TW Hsinchu
- 代理机构: Hauptman Ham, LLP
- 主分类号: G11C17/16
- IPC分类号: G11C17/16 ; G06F30/392 ; G11C17/18 ; H01L23/525 ; H01L27/02 ; H01L27/112 ; G06F119/18
摘要:
An IC structure includes a bit line extending in a first direction, first and second pluralities of FinFETs, and a plurality of eFuses. The FinFETs of the first plurality of FinFETs alternate with the FinFETs of the second plurality of FinFETs along the bit line, each eFuse of the plurality of eFuses includes a conductive segment extending between first and second contact regions, the first contact region is electrically connected to the bit line, and the second contact region is electrically connected to each of an adjacent FinFET of the first plurality of FinFETs and an adjacent FinFET of the second plurality of FinFETs.
公开/授权文献
- US20220093196A1 EFUSE CIRCUIT, METHOD, LAYOUT, AND STRUCTURE 公开/授权日:2022-03-24
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