A method for producing a plurality of chips each comprising an individualisation region, each chip comprising at least: a first and a second level of the electrical tracks, and an interconnections level comprising vias. The method includes producing on the dielectric layer covering the first level a mask having openings located in line with the electrical tracks and making the dielectric layer accessible. The method includes producing, in a region of the chip comprising the individualisation region, patterns conformed so that: first openings of the hard mask are not masked by the patterns, and second openings of the hard mask are masked by the patterns. The method includes producing via openings in the dielectric layer in line solely with the first openings. The method further includes filling in the via openings with an electrically conductive material, and producing the second level of the electrical tracks on the vias.