A stage including: an output circuit connected to a first node and a second node; an input connected to a third node and a fourth node; and a plurality of signal processors between the output and the input, the plurality of signal processors electrically connecting the first node and the third node and electrically connecting the second node and the fourth node, wherein the input includes: a seventh transistor connected between a first input terminal and the fourth node and having a gate electrode connected to a second input terminal; a plurality of eighth transistors serially connected between the third node and the second input terminal and having gate electrodes connected to the fourth node; and a ninth transistor connected between the third node and a second power source and having a gate electrode connected to the second input terminal.