Invention Grant
- Patent Title: Trench isolation for advanced integrated circuit structure fabrication
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Application No.: US17151083Application Date: 2021-01-15
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Publication No.: US11640985B2Publication Date: 2023-05-02
- Inventor: Michael L. Hattendorf , Curtis Ward , Heidi M. Meyer , Tahir Ghani , Christopher P. Auth
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L21/762
- IPC: H01L21/762 ; H01L27/092 ; H01L29/06 ; H01L21/8238 ; H01L29/66 ; H01L29/78 ; H01L27/088 ; H01L21/8234 ; H01L21/768 ; H01L23/522 ; H01L23/532 ; H01L29/165 ; H01L29/417 ; H01L21/033 ; H01L21/28 ; H01L21/285 ; H01L21/308 ; H01L21/311 ; H01L23/528 ; H01L27/11 ; H01L49/02 ; H01L29/08 ; H01L29/51 ; H01L27/02 ; H01L21/02 ; H01L29/167 ; H01L23/00
Abstract:
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon, the fin having a lower fin portion and an upper fin portion. A first insulating layer is directly on sidewalls of the lower fin portion of the fin, wherein the first insulating layer is a non-doped insulating layer comprising silicon and oxygen. A second insulating layer is directly on the first insulating layer directly on the sidewalls of the lower fin portion of the fin, the second insulating layer comprising silicon and nitrogen. A dielectric fill material is directly laterally adjacent to the second insulating layer directly on the first insulating layer directly on the sidewalls of the lower fin portion of the fin.
Public/Granted literature
- US20210143051A1 TRENCH ISOLATION FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION Public/Granted day:2021-05-13
Information query
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