A semiconductor device includes a memory cell array including a plurality of memory blocks, a control logic, a level shifter configured to generate a first internal voltage and a second internal voltage lower than the first internal voltage using a received external voltage on the basis of a control signal from the control logic, and a row decoder configured to provide the first and second internal voltages generated by the level shifter to the memory cell array. The level shifter generates the first internal voltage using the external voltage, generates the second internal voltage using the generated first internal voltage in a power-up mode of the semiconductor device, and generates the second internal voltage using the external voltage in a standby mode of the semiconductor device.