Invention Grant
- Patent Title: Enabling secure state-clean during configuration of partial reconfiguration bitstreams on FPGA
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Application No.: US17129250Application Date: 2020-12-21
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Publication No.: US11651111B2Publication Date: 2023-05-16
- Inventor: Alpa Trivedi , Scott Weber , Steffen Schulz , Patrick Koeberl
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Mendonsa & Hamilton LLP
- Agent Jaffery Watson
- Main IPC: G06F21/76
- IPC: G06F21/76 ; G06F21/57 ; G06F21/53 ; G06F21/30 ; G06F21/85 ; G06F30/398 ; G06N3/04 ; H04L9/08 ; G06F9/30 ; G06F9/50 ; G06F15/177 ; G06F15/78 ; H04L9/40 ; G06F11/07 ; G06F30/331 ; G06F9/38 ; G06F11/30 ; G06F119/12 ; G06N3/08 ; H04L9/00 ; G06F111/04 ; G06F30/31 ; G06F21/73 ; G06F21/74 ; G06N20/00 ; G06F21/71 ; G06F21/44

Abstract:
An apparatus to facilitate enabling secure state-clean during configuration of partial reconfiguration bitstreams on accelerator devices is disclosed. The apparatus includes a security engine to receive an incoming partial reconfiguration (PR) bitstream corresponding to a new PR persona to configure a region of the apparatus; perform, as part of a PR configuration sequence for the new PR persona, a first clear operation to clear previously-set persona configuration bits in the region; perform, as part of the PR configuration sequence subsequent to the first clear operation, a set operation to set new persona configuration bits in the region; and perform, as part of the PR configuration sequence, a second clear operation to clear memory blocks of the region that became unfrozen subsequent to the set operation, the second clear operation performed using a persona-dependent mask corresponding to the new PR persona.
Public/Granted literature
- US20210110069A1 ENABLING SECURE STATE-CLEAN DURING CONFIGURATION OF PARTIAL RECONFIGURATION BITSTREAMS ON FPGA Public/Granted day:2021-04-15
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