Invention Grant
- Patent Title: Method for converting a floating gate non-volatile memory cell to a read-only memory cell and circuit structure thereof
-
Application No.: US16863856Application Date: 2020-04-30
-
Publication No.: US11665915B2Publication Date: 2023-05-30
- Inventor: Fabio De Santis , Vikas Rana
- Applicant: STMicroelectronics International N.V. , STMicroelectronics S.r.l.
- Applicant Address: NE Schiphol
- Assignee: STMicroelectronics International N.V.,STMicroelectronics S.r.l.
- Current Assignee: STMicroelectronics International N.V.,STMicroelectronics S.r.l.
- Current Assignee Address: CH Geneva; IT Agrate Brianza
- Agency: Seed Intellectual Property Law Group LLP
- The original application number of the division: US15908575 2018.02.28
- Main IPC: H01L27/105
- IPC: H01L27/105 ; H01L27/11521 ; H01L27/112 ; G11C29/00 ; H01L27/11519 ; H01L27/11558 ; G11C16/04 ; H01L21/66

Abstract:
According to principles as discussed herein, an EEPROM cell is provided and then, after testing the code, using the exact same architecture, transistors, memory cells, and layout, the EEPROM cell is converted to a read-only memory (“ROM”) cell. This conversion is done on the very same integrated circuit die using the same layout, design, and timing with only a single change in an upper level mask in the memory array. In one embodiment, the mask change is the via mask connecting metal 1 to poly. This allows the flexibility to store the programming code as non-volatile memory code, and then after it has been tested, at time selected by the customer, some or all of that code from a code that can be written to a read-only code that is stored in a ROM cell that is composed the same transistors and having the same layout.
Public/Granted literature
Information query
IPC分类: