A memory device includes a page cache comprising a cache register, a memory array configured with a plurality of memory planes, and control logic, operatively coupled with the memory array. The control logic receives, from a requestor, a cache release command indicating that data associated with a first subset of the plurality of memory planes and pertaining to a previous read command was received by the requestor. Responsive to the cache release command, the control logic returns to the requestor, data from the cache register and associated with a second subset of the plurality of memory planes and pertaining to the previous read command, while concurrently copying data associated with the first subset of the plurality of memory planes and pertaining to a subsequent read command into the cache register.