Invention Grant
- Patent Title: Methods and systems for congestion prediction in logic synthesis using graph neural networks
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Application No.: US17334657Application Date: 2021-05-28
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Publication No.: US11675951B2Publication Date: 2023-06-13
- Inventor: Amur Ghose , Yingxue Zhang , Zhanguang Zhang
- Applicant: Amur Ghose , Yingxue Zhang , Zhanguang Zhang
- Applicant Address: CA Montreal
- Assignee: HUAWEI TECHNOLOGIES CO., LTD.
- Current Assignee: HUAWEI TECHNOLOGIES CO., LTD.
- Current Assignee Address: CN Shenzhen
- Main IPC: G06F30/392
- IPC: G06F30/392 ; G06F30/398 ; G06N3/08 ; G06F18/20 ; G06F18/213 ; G06F18/21

Abstract:
Method and system for assisting electronic chip design, comprising: receiving netlist data for a proposed electronic chip design, the netlist data including a list of circuit elements and a list of interconnections between the circuit elements; converting the netlist data to a graph that represents at least some of the circuit elements as nodes and represents the interconnections between the circuit elements as edges; extracting network embeddings for the nodes based on a graph topology represented by the edges; extracting degree features for the nodes based on the graph topology; and computing, using a graph neural network, a congestion prediction for the circuit elements that are represented as nodes based on the extracted network embeddings and the extracted degree features.
Public/Granted literature
- US20220405455A1 METHODS AND SYSTEMS FOR CONGESTION PREDICTION IN LOGIC SYNTHESIS USING GRAPH NEURAL NETWORKS Public/Granted day:2022-12-22
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