Invention Grant
- Patent Title: Techniques for non-consecutive logical addresses
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Application No.: US17580333Application Date: 2022-01-20
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Publication No.: US11687291B2Publication Date: 2023-06-27
- Inventor: Hua Tan , Fangwen Zhou , Wenjing Chen
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Holland & Hart LLP
- Main IPC: G06F3/06
- IPC: G06F3/06 ; G06F12/02

Abstract:
Methods, systems, and devices for memory operations are described. A first set of commands may be received for accessing a memory device. The first set of commands may include non-consecutive logical addresses that correspond to consecutively indexed physical addresses. A determination that the non-consecutive logical addresses correspond to consecutively indexed physical addresses may be determined based on a first mapping stored in a volatile memory. A second mapping may be transferred to the volatile memory based on the determination. The second mapping may include an indication of whether information stored at a set of physical address is valid. A second set of commands including non-consecutive logical addresses may be received for accessing the memory device. Data for the second set of commands that include the non-consecutive logical addresses may be retrieved from the memory device using the second mapping.
Public/Granted literature
- US20230046402A1 TECHNIQUES FOR NON-CONSECUTIVE LOGICAL ADDRESSES Public/Granted day:2023-02-16
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