Invention Grant
- Patent Title: Methods and apparatus to calibrate a dual-residue pipeline analog to digital converter
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Application No.: US17515041Application Date: 2021-10-29
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Publication No.: US11689210B2Publication Date: 2023-06-27
- Inventor: Prasanth K , Srinivas Kumar Reddy Naru , Visvesvaraya Appala Pentakota
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Valerie M. Davis; Frank D. Cimino
- Main IPC: H03M1/10
- IPC: H03M1/10

Abstract:
An example apparatus includes: an analog input; a resistor circuit including a first reference output and a second reference output; a first amplifier including a first analog input, a first reference input, and a first amplifier output, the first analog input coupled to the analog input, the first reference input coupled to the first reference output; a second amplifier including a second analog input, a second reference input, and a second amplifier output, the second analog input coupled to the analog input, the second reference input coupled to the second reference output; a first comparator including a first comparator input, the first comparator input coupled to the first amplifier output; and a second comparator including a second comparator input, the second comparator input coupled to the second amplifier output; a first multiplexer including a first multiplexer input and a first residue output, the first multiplexer input coupled to the first amplifier output; and a second multiplexer including a second multiplexer input and a second residue output, the second multiplexer input coupled to the second amplifier output.
Public/Granted literature
- US20230138266A1 METHODS AND APPARATUS TO CALIBRATE A DUAL-RESIDUE PIPELINE ANALOG TO DIGITAL CONVERTER Public/Granted day:2023-05-04
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