In some examples, a quad flat no lead (QFN) semiconductor package comprises a flip chip semiconductor die having a surface and circuitry formed in the surface; and a conductive pillar coupled to the semiconductor die surface. The conductive pillar has a distal end relative to the semiconductor die, the distal end having a cavity including a cavity floor and one or more cavity walls circumscribing the cavity floor. The one or more cavity walls are configured to contain solder.