Invention Grant
- Patent Title: Facilitating sequential reads in memory sub-systems
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Application No.: US17521360Application Date: 2021-11-08
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Publication No.: US11704256B2Publication Date: 2023-07-18
- Inventor: Stephen Hanna , Nadav Grosz
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Lowenstein Sandler LLP
- Main IPC: G06F12/14
- IPC: G06F12/14 ; G06F1/24 ; G06F12/02 ; G06F12/06 ; G06F21/79 ; G06F3/06

Abstract:
An example memory subsystem includes a memory component and a processing device, operatively coupled to the memory component. The processing device is configured to receive a plurality of logical-to-physical (L2P) records, wherein an L2P record of the plurality of L2P records maps a logical block address to a physical address of a memory block on the memory component; determine a sequential assist value specifying a number of logical block addresses that are mapped to consecutive physical addresses sequentially following the physical address specified by the L2P record; generate a security token encoding the sequential assist value; and associate the security token with the L2P record.
Public/Granted literature
- US20220058138A1 FACILITATING SEQUENTIAL READS IN MEMORY SUB-SYSTEMS Public/Granted day:2022-02-24
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