Invention Grant
- Patent Title: Parallelization of GPU composition with DPU topology selection
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Application No.: US17449630Application Date: 2021-09-30
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Publication No.: US11705091B2Publication Date: 2023-07-18
- Inventor: Sushil Chauhan , Mahesh Aia , Dileep Marchya
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Procopio, Cory, Hargreaves & Savitch
- Main IPC: G09G5/377
- IPC: G09G5/377 ; G06T1/20

Abstract:
This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for parallelization of GPU composition with DPU topology selection. A processor may receive an indication of a plurality of application layers for composition at a first processor (e.g., a DPU) and a second processor (e.g., a GPU). The processor may select one or more first application layers of the plurality of application layers for attempted composition at the first processor and one or more second application layers of the plurality of application layers for composition at the second processor. The processor may transmit each of the one or more first application layers to the first processor for composition and each of the one or more second application layers to the second processor for composition.
Public/Granted literature
- US20230096035A1 PARALLELIZATION OF GPU COMPOSITION WITH DPU TOPOLOGY SELECTION Public/Granted day:2023-03-30
Information query
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