Invention Grant
- Patent Title: Structure and method for preventing silicide contamination during the manufacture of micro-processors with embedded flash memory
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Application No.: US17094758Application Date: 2020-11-10
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Publication No.: US11706917B2Publication Date: 2023-07-18
- Inventor: Meng-Han Lin , Wei Cheng Wu
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Seed IP Law Group LLP
- The original application number of the division: US16282045 2019.02.21
- Main IPC: H10B41/47
- IPC: H10B41/47 ; H01L29/423 ; H01L21/285 ; H01L29/788 ; H01L21/306 ; H01L29/66 ; H10B41/30 ; H10B99/00

Abstract:
A method is provided in which a monitor cell is made that is substantially identical to the flash memory cells of an embedded memory array. The monitor cell is formed simultaneously with the cells of the memory array, and so in certain critical aspects, is exactly comparable. An aperture is formed that extends through the control gate and intervening dielectric to the floating gate of the monitor cell. To prevent silicide contamination during a subsequent CMP process, a silicide protection layer (SPL), such as a resist protective oxide, is formed over exposed portions of the control gate prior to formation of a silicide contact formed on the floating gate. The SPL is formed simultaneously with existing manufacturing processes to avoid additional process steps.
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