Invention Grant
- Patent Title: Decoupling layer to reduce underfill stress in semiconductor devices
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Application No.: US16554789Application Date: 2019-08-29
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Publication No.: US11715928B2Publication Date: 2023-08-01
- Inventor: Priyanka Dobriyal , Susheel G. Jadhav , Ankur Agrawal , Quan A. Tran , Raiyomand F. Aspandiar , Kenneth M. Brown
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williams & Wyatt, P.C.
- Main IPC: H01S5/0234
- IPC: H01S5/0234 ; G02F1/015 ; H01S5/0237 ; H01S5/02234 ; H01S5/02325 ; H01S5/026

Abstract:
An integrated circuit assembly includes a support (e.g., package substrate or circuit board) and a semiconductor die including a device. The semiconductor die is mounted to the support with the device facing the support. The device can be, for example, a quantum well laser device or a photonics device. A layer of decoupling material is on the device. An underfill material is between the semiconductor die and the support, where the decoupling material is between the device and the underfill material. The decoupling layer decouples stress from transferring from the underfill material into the device. For example, the decoupling material forms only weak bonds with the underfill material and/or a passivation layer on the device, in an embodiment. Weak bonds include non-covalent bonds and non-ionic bonds, for example. The decoupling material can be, for instance, a PTFE film, a poly(p-xylylene) film, a fluorocarbon, or a compound lacking free hydroxyl groups.
Public/Granted literature
- US20210066882A1 DECOUPLING LAYER TO REDUCE UNDERFILL STRESS IN SEMICONDUCTOR DEVICES Public/Granted day:2021-03-04
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