A 3D semiconductor memory device includes a peripheral circuit structure on a first substrate, a second substrate on the peripheral circuit structure, an electrode structure on the second substrate, the electrode structure comprising stacked electrodes, and a vertical channel structure penetrating the electrode structure. The peripheral circuit structure includes a dummy interconnection structure under the second substrate. The dummy interconnection structure includes stacked interconnection lines, and a via connecting a top surface of an uppermost one of the interconnection lines to a bottom surface of the second substrate.