Coupled semiconductor package
Abstract:
Provided is a coupled semiconductor package including at least two substrate pads; at least one semiconductor chip installed on each of the substrate pads; at least one terminal each of which is electrically connected to each substrate pad and each semiconductor chip; and a package housing covering a part of the at least one semiconductor chip and the at least one terminal, wherein lower surfaces of one or more substrate pads are formed to be electrically connected and lower surfaces of another one or more substrate pads are formed to be electrically insulated. Accordingly, partial insulation may be economically realized without applying an insulating material to a heat sink, when the package is joined to the heat sink.
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