Invention Grant
- Patent Title: Method of manufacturing three dimensional semiconductor device including first and second channels and buried insulation and conductive patterns
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Application No.: US17540688Application Date: 2021-12-02
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Publication No.: US11723203B2Publication Date: 2023-08-08
- Inventor: Eun Yeoung Choi , Hyung Joon Kim , Su Hyeong Lee , Yong Seok Cho
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Suwon-si
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Gyeonggi-Do
- Agency: Harness, Dickey & Pierce, P.L.C.
- Priority: KR 20190064724 2019.05.31
- Main IPC: H10B43/27
- IPC: H10B43/27 ; H10B41/27

Abstract:
A semiconductor device includes a plurality of first gate electrodes sequentially stacked on a substrate, a second gate electrode on the plurality of first gate electrodes, a first channel structure extending through the plurality of first gate electrodes and a portion of the second gate electrode, a buried insulation pattern on a sidewall of the first channel structure, of which an upper surface is at a higher level than a top end of the first channel structure, a second channel structure extending through a remainder of the second gate electrode, the second channel structure connected to the first channel structure, and a buried conductive pattern on a sidewall of the second channel structure.
Public/Granted literature
- US20220093642A1 THREE DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME Public/Granted day:2022-03-24
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