Invention Grant
- Patent Title: Method for fabricating a strained semiconductor-on-insulator substrate
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Application No.: US17207202Application Date: 2021-03-19
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Publication No.: US11728207B2Publication Date: 2023-08-15
- Inventor: Walter Schwarzenbach , Guillaume Chabanne , Nicolas Daval
- Applicant: Soitec
- Applicant Address: FR Bernin
- Assignee: Soitec
- Current Assignee: Soitec
- Current Assignee Address: FR Bernin
- Agency: TraskBritt
- Priority: FR 54369 2016.05.17
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/762

Abstract:
A method for fabricating a strained semiconductor-on-insulator substrate comprises bonding a donor substrate to a receiving substrate with a dielectric layer at the interface. The donor substrate comprises a monocrystalline carrier substrate, an intermediate etch-stop layer, and a monocrystalline semiconductor layer. The monocrystalline semiconductor layer is transferred from the donor substrate to the receiving substrate. Trench isolations are formed to cut a portion from a layer stack including the transferred monocrystalline semiconductor layer, the dielectric layer, and the strained semiconductor material layer. The cutting operation results in relaxation of strain in the strained semiconductor material, and in application of strain to the transferred monocrystalline semiconductor layer. After transferring the monocrystalline semiconductor layer and before the cutting operation, a portion of the carrier substrate is selectively etched with respect to the intermediate layer, and the intermediate layer is selectively etched with respect to the monocrystalline semiconductor layer.
Public/Granted literature
- US20210225695A1 METHOD FOR FABRICATING A STRAINED SEMICONDUCTOR-ON-INSULATOR SUBSTRATE Public/Granted day:2021-07-22
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