All levels dynamic start voltage programming of a memory device in a memory sub-system
Abstract:
Control logic in a memory device identifies a set of a plurality of memory cells configured as multi-level cell (MLC) memory to be programmed during a program operation and causes one or more programming pulses to be applied to the set of the plurality of memory cells configured as MLC memory to program memory cells in the set of memory cells configured as MLC memory to respective programming levels of a plurality of programming levels as part of the program operation. Responsive to the one or more programming pulses being applied, the control logic further performs a program verify operation to verify whether the memory cell in the set of memory cells configured as MLC memory were programmed to the respective programming levels of the plurality of programming levels.
Information query
Patent Agency Ranking
0/0