Invention Grant
- Patent Title: Method for inducing stress in semiconductor devices
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Application No.: US17348267Application Date: 2021-06-15
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Publication No.: US11757039B2Publication Date: 2023-09-12
- Inventor: Gaspard Hiblot , Geert Van der Plas
- Applicant: IMEC VZW
- Applicant Address: BE Leuven
- Assignee: IMEC VZW
- Current Assignee: IMEC VZW
- Current Assignee Address: BE Leuven
- Agency: McDonnell Boehnen Hulbert & Berghoff LLP
- Priority: EP 181930 2020.06.24
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L21/8238 ; H01L23/48 ; H01L27/092

Abstract:
Example embodiments relate to methods for inducing stress in semiconductor devices. One method includes a method for producing a first semiconductor device and a second semiconductor device configured to conduct current through the controlled density of charge carriers in a channel area. The charge carriers of the first semiconductor device have opposite polarity to the charge carriers of the second semiconductor device. The method includes producing a stress relaxed buffer (SRD) layer. The back side of the SRB layer is positioned on a substrate. The method also includes producing a semiconductor layer on the front side of the SRB layer. Additionally, the method includes producing the first semiconductor device and the second semiconductor device on the semiconductor layer, removing the substrate, thinning the SRB layer, producing a cavity in the SRB layer, and filling the cavity with a material to create a stress compensation area.
Public/Granted literature
- US20210408287A1 Method for Inducing Stress in Semiconductor Devices Public/Granted day:2021-12-30
Information query
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