Invention Grant
- Patent Title: Voltage based combining of block families for memory devices
-
Application No.: US17868124Application Date: 2022-07-19
-
Publication No.: US11768619B2Publication Date: 2023-09-26
- Inventor: Michael Sheperek , Kishore Kumar Muchherla , Shane Nowell
- Applicant: MICRON TECHNOLOGY, INC.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Lowenstein Sandler LLP
- Main IPC: G06F3/06
- IPC: G06F3/06

Abstract:
An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to identify a first block family comprising a first set of blocks, wherein the first block family comprises a plurality of blocks that have been programmed within at least one of a specified time window or a specified temperature window; identify a second block family comprising a second set of blocks; and responsive to a determining that a threshold criterion is satisfied, combine the first block family and the second block family by appending, to first block family metadata of the first block family, a record referencing the second set of blocks.
Public/Granted literature
- US20220350488A1 VOLTAGE BASED COMBINING OF BLOCK FAMILIES FOR MEMORY DEVICES Public/Granted day:2022-11-03
Information query