Invention Grant
- Patent Title: Semiconductor structure having an anti-arcing pattern disposed on a passivation layer and a post passivation layer disposed on the anti-arcing pattern
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Application No.: US17667564Application Date: 2022-02-09
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Publication No.: US11769704B2Publication Date: 2023-09-26
- Inventor: Sheng-An Kuo , Ching-Jung Yang , Hsien-Wei Chen , Jie Chen , Ming-Fa Chen
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: JCIPRNET
- Main IPC: H01L23/31
- IPC: H01L23/31 ; H01L21/56 ; H01L23/498 ; H01L23/538 ; H01L25/065 ; H01L23/00

Abstract:
A semiconductor structure including a first semiconductor die, a second semiconductor die, a passivation layer, an anti-arcing pattern, and conductive terminals is provided. The second semiconductor die is stacked over the first semiconductor die. The passivation layer covers the second semiconductor die and includes first openings for revealing pads of the second semiconductor die. The anti-arcing pattern is disposed over the passivation layer. The conductive terminals are disposed over and electrically connected to the pads of the second semiconductor die.
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Information query
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