Invention Grant
- Patent Title: Static power reduction in caches using deterministic Naps
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Application No.: US17541776Application Date: 2021-12-03
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Publication No.: US11775046B2Publication Date: 2023-10-03
- Inventor: Oluleye Olorode , Mehrdad Nourani
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Michael T. Gabrik; Frank D. Cimino
- The original application number of the division: US14694285 2015.04.23
- Main IPC: G06F1/3234
- IPC: G06F1/3234 ; G06F12/0811 ; G06F12/0895 ; G06F12/0846

Abstract:
Disclosed embodiments relate to a dNap architecture that accurately transitions cache lines to full power state before an access to them. This ensures that there are no additional delays due to waking up drowsy lines. Only cache lines that are determined by the DMC to be accessed in the immediate future are fully powered while others are put in drowsy mode. As a result, we are able to significantly reduce leakage power with no cache performance degradation and minimal hardware overhead, especially at higher associativities. Up to 92% static/Leakage power savings are accomplished with minimal hardware overhead and no performance tradeoff.
Public/Granted literature
- US20220091659A1 STATIC POWER REDUCTION IN CACHES USING DETERMINISTIC NAPS Public/Granted day:2022-03-24
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