There is provided a gate driving circuit including cascaded Gate Driver On Array (GOA) units, each GOA unit drives a row of pixels and includes a starting sub-unit, an output sub-unit and an output terminal, in the GOA unit at a first stage, the starting sub-unit is coupled with a starting signal, a first control signal, a second control signal and a constant voltage potential, and the output sub-unit is coupled with a first clock signal and a first power supply signal; in the GOA unit at an nth stage, the starting sub-unit is coupled with the starting signal, the first control signal, the second control signal and the output terminal of the GOA unit at an (n−1)th stage, the output sub-unit is coupled with the first power supply signal and the output terminal of the GOA unit at an (n+1)th stage, n is an integer greater than 1.