A display includes a display area having pixels arranged along a first direction and a second direction crossing the first direction over a substrate. Gate lines, data lines, and reference voltage lines are disposed at the display area and are coupled to the pixels. A gate driving circuit includes stage circuit units disposed at the display area and coupled to each of the gate lines. The stage circuit units include branch circuits divisionally disposed between the pixels along the first direction and a branch network disposed at a network line formation portion positioned at one side of each of the pixels disposed along the first direction. The branch network includes control node lines and network lines selectively coupled to the branch circuits. An additional pattern portion is disposed at the network line formation portion to overlap a reference voltage line disposed at each of some of the pixels.