Invention Grant
- Patent Title: Nanosheet transistors with different gate materials in same stack and method of making
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Application No.: US17212311Application Date: 2021-03-25
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Publication No.: US11776856B2Publication Date: 2023-10-03
- Inventor: Mark Douglas Hall , Tushar Praful Merchant , Anirban Roy
- Applicant: NXP B.V.
- Applicant Address: NL Eindhoven
- Assignee: NXP B.V.
- Current Assignee: NXP B.V.
- Current Assignee Address: NL Eindhoven
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L27/092 ; H01L29/423 ; H01L29/06

Abstract:
A semiconductor device and fabrication method are described for integrating stacked top and bottom nanosheet transistors by providing a nanosheet transistor stack having bottom and top Si/SiGe superlattice structures (11-14, 17-20) which are separated from one another by a barrier oxide layer (15) and which are separately processed to form bottom gate electrodes having a first gate structure (40A-B) in the bottom Si/SiGe superlattice structures and to form top gate electrodes having a second, different gate structure (46A-B) in the top Si/SiGe superlattice structures.
Public/Granted literature
- US20220310456A1 Nanosheet Transistors with Different Gate Materials in Same Stack and Method of Making Public/Granted day:2022-09-29
Information query
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