Invention Grant
- Patent Title: Transistors having vertical nanostructures
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Application No.: US17133290Application Date: 2020-12-23
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Publication No.: US11777033B2Publication Date: 2023-10-03
- Inventor: Pei-Hsun Wang , Chun-Hsiung Lin , Cheng-Ting Chung , Chih-Hao Wang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: HAYNES AND BOONE, LLP
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/06 ; H01L29/66 ; H01L21/8234
Abstract:
A semiconductor device according to the present disclosure includes a first isolation feature and a second isolation feature, a fin structure extending lengthwise along a first direction and sandwiched between the first isolation feature and the second isolation feature along a second direction perpendicular to the first direction, a first channel member disposed over the first isolation feature, a second channel member disposed over the second isolation feature, and a gate structure disposed over and wrapping around the first channel member and the second channel member.
Public/Granted literature
- US20210273104A1 TRANSISTORS HAVING VERTICAL NANOSTRUCTURES Public/Granted day:2021-09-02
Information query
IPC分类:
