Invention Grant
- Patent Title: Semiconductor package including vertical interconnector
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Application No.: US17154705Application Date: 2021-01-21
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Publication No.: US11784162B2Publication Date: 2023-10-10
- Inventor: Tae Hoon Kim , Chae Sung Lee
- Applicant: SK hynix Inc.
- Applicant Address: KR Icheon-si
- Assignee: SK hynix Inc.
- Current Assignee: SK hynix Inc.
- Current Assignee Address: KR Icheon-si
- Agency: WILLIAM PARK & ASSOCIATES LTD.
- Priority: KR 20200103950 2020.08.19
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L23/31 ; H01L23/498 ; H01L23/00

Abstract:
A semiconductor package includes at least one semiconductor chip disposed in such a way that an active surface with chip pads faces a redistribution layer, vertical interconnectors extending in a vertical direction from the chip pads toward the redistribution layer, wherein each of the vertical connectors has a first end portion that is connected to a corresponding chip pad and a second end portion that is disposed on an opposite end of each vertical interconnector in relation to the first end portion, and a molding layer covering the semiconductor chip and the vertical interconnectors while exposing a surface of each of the second end portions of the vertical interconnectors, wherein the redistribution layer is formed over the molding layer, the redistribution layer having a redistribution land that is in contact with the surface of the second end portion, and wherein a width of the surface of the second end portion is greater than a width of an extension portion between the first end portion and the second end portion of each vertical interconnector.
Public/Granted literature
- US20220059503A1 SEMICONDUCTOR PACKAGE INCLUDING VERTICAL INTERCONNECTOR Public/Granted day:2022-02-24
Information query
IPC分类: