An array substrate, includes: a substrate, a first metal layer, a first buffer layer, and an active layer, a gate insulating layer, a second metal layer, a first insulating layer, a third metal layer and a first planarization layer. The first metal layer is electrically connected with the first doped area of the active layer through the bridge layer of the second metal layer. The third metal layer is electrically connected with the second doped area of the active layer. The array substrate of the present disclosure reduces a size of a thin film transistor by stacking the first metal layer, the second metal layer, and the third metal layer, thereby increasing pixel density. A display panel is also provided.