Invention Grant
- Patent Title: Devices and methods for signal integrity protection technique
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Application No.: US16451557Application Date: 2019-06-25
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Publication No.: US11798894B2Publication Date: 2023-10-24
- Inventor: Bok Eng Cheah , Jackson Chung Peng Kong , Khang Choong Yong , Kooi Chi Ooi , Min Suet Lim
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Compass IP Law PC
- Priority: MY 2018703902 2018.10.22
- Main IPC: H01L21/48
- IPC: H01L21/48 ; H01L23/498 ; H01L23/00 ; H01L23/552

Abstract:
The technique described herein includes a device to address the electrical performance (e.g. signal integrity) degradation ascribed to electromagnetic interference and/or crosstalk coupling occur at tightly coupled (e.g. about 110 μm pitch or less) interconnects, including the first level (e.g. the interconnection between a die and a package substrate). In some embodiments, this invention provides a conductive layer with a plurality of cavities to isolate electromagnetic coupling and/or interference between adjacent interconnects for electronic device performance scaling. In some embodiments, at least one interconnect joint is coupled to the conductive layer, and at least one interconnect joint is isolated from the conductive layer by a dielectric lining at least one of the cavities, the conductive layer being associated to a ground reference voltage by the interconnect joint coupled to the conductive layer.
Information query
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