- 专利标题: Instruction prefetch mechanism
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申请号: US17210867申请日: 2021-03-24
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公开(公告)号: US11803476B2公开(公告)日: 2023-10-31
- 发明人: Vasileios Porpodas , Guei-Yuan Lueh , Subramaniam Maiyuran , Wei-Yu Chen
- 申请人: Intel Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: INTEL CORPORATION
- 当前专利权人: INTEL CORPORATION
- 当前专利权人地址: US CA Santa Clara
- 代理机构: JAFFERY WATSON MENDONSA & HAMILTON LLP
- 主分类号: G06F12/0862
- IPC分类号: G06F12/0862 ; G06F12/0875 ; G06F9/30 ; G06F8/41
摘要:
An apparatus to facilitate data prefetching is disclosed. The apparatus includes a cache, one or more execution units (EUs) to execute program code, prefetch logic to maintain tracking information of memory instructions in the program code that trigger a cache miss and compiler logic to receive the tracking information, insert one or more pre-fetch instructions in updated program code to prefetch data from a memory for execution of one or more of the memory instructions that triggered a cache miss and download the updated program code for execution by the one or more EUs.
公开/授权文献
- US20210279177A1 INSTRUCTION PREFETCH MECHANISM 公开/授权日:2021-09-09
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