Invention Grant
- Patent Title: Method of forming package substrate with partially recessed capacitor
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Application No.: US17707872Application Date: 2022-03-29
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Publication No.: US11804382B2Publication Date: 2023-10-31
- Inventor: Jaimal Mallory Williamson , Snehamay Sinha
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Dawn Jos; Frank D. Cimino
- The original application number of the division: US16795873 2020.02.20
- Main IPC: H01L21/48
- IPC: H01L21/48 ; H01L23/498 ; H01L23/64 ; H01L23/00

Abstract:
A semiconductor package includes a multilayer substrate including a dielectric layer, a first conductive layer forming a first set of electrical contacts, a second conductive layer forming package electrical contacts and two capacitor electrical contacts, conductive vias extending through the dielectric layer between the first conductive layer with the second conductive layer, and a solder mask layer over the second conductive layer. The semiconductor package further includes a semiconductor die on the first side of the multilayer substrate electrically connected a capacitor on the second side of the multilayer substrate. A recessed portion of the capacitor is within a capacitor opening of the solder mask layer between the two capacitor electrical contacts and a board-side surface of the solder mask layer.
Public/Granted literature
- US20220223509A1 PACKAGE SUBSTRATE WITH PARTIALLY RECESSED CAPACITOR Public/Granted day:2022-07-14
Information query
IPC分类: