A Peripheral Component Interconnect Express (PCIe) interface device includes a PCIe layer and a PCIe controller. The PCIe layer performs communication between a host and a Direct Memory Access (DMA) device. The PCIe controller switches an operating clock from a PCIe clock generated based on a reference clock to an internal clock, processes data of the PCIe layer on the basis of the internal clock, and recovers a link with respect to the host, when a reset signal received from the host is asserted or the reference clock is off.