A circuit for reading or writing a RAM includes a shift register coupled to the RAM, a test data input, and a test data output. The circuit further includes a control circuit configured to generate a pulse every N clock cycles, each pulse triggering a RAM access operation transferring data between the shift register and the RAM, N being equal to a data width of the RAM divided by a parallel factor, the parallel factor being a number of pins in either the test data input or the test data output configured for parallel data loading.