A display device that includes pixel circuits, in each of which a plurality of types of transistors coexist, and that operates normally is implemented while suppressing an increase in processing cost.
Each unit circuit includes a first control circuit (311), a first output circuit (321), and a second output circuit (322). The first output circuit (321) includes a first output terminal (38) connected to a first scanning signal line; a P-type transistor (M4) having a control terminal connected to a first internal node (N1), a first conductive terminal to which a gate high potential (VGH) is provided, and a second conductive terminal connected to the first output terminal (38); and a N-type transistor (M5) having a control terminal connected to the first internal node (N1), a first conductive terminal connected to the first output terminal (38), and a second conductive terminal to which a gate low potential (VGL) is provided.