Invention Grant
- Patent Title: Lateral bipolar junction transistor including a stress layer and method
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Application No.: US17555561Application Date: 2021-12-20
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Publication No.: US11837653B2Publication Date: 2023-12-05
- Inventor: Jagar Singh , Alexander M. Derrickson , Alvin J. Joseph , Andreas Knorr , Judson R. Holt
- Applicant: GlobalFoundries U.S. Inc.
- Applicant Address: US NY Malta
- Assignee: GlobalFoundries U.S. Inc.
- Current Assignee: GlobalFoundries U.S. Inc.
- Current Assignee Address: US NY Malta
- Agency: Hoffman Warnick LLC
- Agent Francois Pagette
- Main IPC: H01L29/73
- IPC: H01L29/73 ; H01L29/737 ; H01L29/08 ; H01L29/66 ; H01L29/10

Abstract:
Disclosed is a semiconductor structure with a lateral bipolar junction transistor (BJT). This semiconductor structure can be readily integrated into advanced silicon-on-insulator (SOI) technology platforms. Furthermore, to maintain or improve upon performance characteristics (e.g., cut-off frequency (fT)/maximum oscillation frequency (fmax) and beta cut-off frequency) that would otherwise be negatively impacted due to changing of the orientation of the BJT from vertical to lateral, the semiconductor structure can further include a dielectric stress layer (e.g., a tensilely strained layer in the case of an NPN-type transistor or a compressively strained layer in the case of a PNP-type transistor) partially covering the lateral BJT for charge carrier mobility enhancement and the lateral BJT can be configured as a lateral heterojunction bipolar transistor (HBT). Also disclosed is a method for forming the semiconductor structure.
Public/Granted literature
- US20230065785A1 LATERAL BIPOLAR JUNCTION TRANSISTOR INCLUDING A STRESS LAYER AND METHOD Public/Granted day:2023-03-02
Information query
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