Invention Grant
- Patent Title: Power semiconductor device and substrate with dimple region
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Application No.: US17732751Application Date: 2022-04-29
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Publication No.: US11842968B2Publication Date: 2023-12-12
- Inventor: Kohei Yabuta , Takayuki Yamada , Yuya Muramatsu , Noriyuki Besshi , Yutaro Sugi , Hiroaki Haruna , Masaru Fuku , Atsuki Fujita
- Applicant: MITSUBISHI ELECTRIC CORPORATION
- Applicant Address: JP Tokyo
- Assignee: MITSUBISHI ELECTRIC CORPORATION
- Current Assignee: MITSUBISHI ELECTRIC CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: BUCHANAN INGERSOLL & ROONEY PC
- Priority: JP 17209200 2017.10.30
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L21/48 ; H01L23/13

Abstract:
A power semiconductor device includes a substrate and a semiconductor element bonded onto a first surface of the substrate through use of a sintered metal bonding material. The substrate has a plurality of dimples formed in the first surface and located outside a location immediately below a heat generation unit of the semiconductor element. The sintered metal bonding material is supplied onto the substrate after the formation of the dimples, and the semiconductor element is bonded to the substrate through application of heat and a pressure thereto.
Public/Granted literature
- US20220254738A1 POWER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR POWER SEMICONDUCTOR DEVICE Public/Granted day:2022-08-11
Information query
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