A signal processing system includes a digital signal processing circuit, a power management unit, and a digital control circuit. The power management unit provides a first voltage to the digital signal processing circuit. When in a calibration mode the digital control circuit controls the power management unit to set the first voltage at a minimum preset value, controls the digital signal processing circuit to operate under a first calibration target frequency, triggers the digital signal processing circuit to perform a built-in self-test, raises the first voltage when the built-in self-test fails, triggers the digital signal processing circuit to perform the built-in self-test again, and stores the first calibration target frequency and a value of the first voltage corresponding to the first calibration target frequency to a non-volatile memory when the built-in self-test has succeeded.