Invention Grant
- Patent Title: Multilayer wiring substrate
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Application No.: US17564120Application Date: 2021-12-28
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Publication No.: US11871513B2Publication Date: 2024-01-09
- Inventor: Masao Kondo , Shigeki Koya , Kenji Sasaki
- Applicant: Murata Manufacturing Co., Ltd.
- Applicant Address: JP Kyoto-fu
- Assignee: Murata Manufacturing Co., Ltd.
- Current Assignee: Murata Manufacturing Co., Ltd.
- Current Assignee Address: JP Kyoto-fu
- Agency: Studebaker & Brackett PC
- Priority: JP 19043951 2019.03.11
- The original application number of the division: US16814902 2020.03.10
- Main IPC: H05K1/02
- IPC: H05K1/02 ; H05K1/11 ; H05K3/24 ; H01L21/48 ; H01L23/538 ; H01L23/467

Abstract:
A cavity elongated in one direction is formed in a protective film covering the conductive pattern of the topmost conductive layer of a multilayer wiring substrate. The cavity exposes part of the conductive pattern. A first via-conductor extends downward from the conductive pattern of the topmost conductive layer at least until that of a second conductive layer. Second via-conductors extend downward from the conductive pattern of the second or third conductive layer at least until that of a conductive layer one below. As viewed from above, the first via-conductor and the cavity partially overlap each other. At least two second via-conductors are disposed to sandwich the cavity therebetween. The difference between the smallest gap between the cavity and the second via-conductor at one side and that between the cavity and the second via-conductor at the other side is smaller than the smallest gap between the cavity and the second via-conductors.
Public/Granted literature
- US20220124908A1 MULTILAYER WIRING SUBSTRATE Public/Granted day:2022-04-21
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