- 专利标题: ESD protection circuit
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申请号: US17989481申请日: 2022-11-17
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公开(公告)号: US11876090B2公开(公告)日: 2024-01-16
- 发明人: David Michael Rogers , Eric N. Mann , Eric Lee Swindlehurst , Toru Miyamae , Timothy John Williams , Ryuta Nagai , Sungkwon Lee , Ravindra M. Kapre , Mimi Xuefeng Zhao Qian , Yan Yi , Dung Si Ho , Boo Chin-Hua
- 申请人: Cypress Semiconductor Corporation
- 申请人地址: US CA San Jose
- 专利权人: Cypress Semiconductor Corporation
- 当前专利权人: Cypress Semiconductor Corporation
- 当前专利权人地址: US CA San Jose
- 主分类号: H01L27/02
- IPC分类号: H01L27/02
摘要:
An electrostatic discharge protection circuit capable of clamping both positive and negative ESD events and passing signals is provided. Generally, the circuit includes a p-channel field-effect transistor (PFET) clamp coupled to a pin to be protected, the PFET clamp including a plurality of PFETs in a DN-well, an n-channel field-effect transistors (NFET) clamp coupled between ground and the pin through the PFET clamp, the NFET clamp including a plurality of NFETs coupled in series, and a bias network for biasing a voltage of the DN well to substantially equal a voltage on the pin when the voltage on the pin is greater than ground potential, and to ground potential when the pin voltage is less than ground potential. The plurality of are PFETs coupled in parallel between the pin and the NFET clamp, each of the PFETs is coupled to the pin though one of a plurality ballast resistors.
公开/授权文献
- US20230343779A1 ESD PROTECTION CIRCUIT 公开/授权日:2023-10-26
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