The signal processing device according to an embodiment of the present disclosure includes: a frame buffer to store an input image and output an output image, an output synchronization signal calculator to calculate an output synchronization signal based on an input synchronization signal and a size or a position of the output image in comparison with the input image, and an output synchronization signal output interface to output a variable output synchronization signal of which a start timing changes based on a signal from the output synchronization signal calculator, wherein a difference between a start timing of the input synchronization signal and a start timing of the output synchronization signal changes based on the size of the output image. Accordingly, a delay time may be reduced in response to the output image having a size different from a size of the input image being output.