Invention Grant
- Patent Title: Non-volatile memory with engineered channel gradient
-
Application No.: US17828685Application Date: 2022-05-31
-
Publication No.: US11881271B2Publication Date: 2024-01-23
- Inventor: Jiacen Guo , Xiang Yang , Xiaochen Zhu
- Applicant: SanDisk Technologies LLC
- Applicant Address: US TX Addison
- Assignee: SanDisk Technologies LLC
- Current Assignee: SanDisk Technologies LLC
- Current Assignee Address: US TX Addison
- Agency: Vierra Magen Marcus LLP
- Main IPC: G11C16/34
- IPC: G11C16/34 ; G11C16/26 ; G11C16/08 ; G11C16/04

Abstract:
To save power during a read process, NAND strings of each sub-block of a block have independently controlled source side select lines connected to source side select gates and drain side select lines connected to drain side select gates so that NAND strings of unselected sub-blocks can float and not draw current. To prevent read disturb in NAND strings of unselected sub-blocks, after all word lines are raised to a pass gate voltage, unselected word lines nearby the selected word line are lowered to respective intermediate voltages while lowering the voltage on the selected word line in order to achieve a channel potential gradient in the floated NAND strings of the unselected sub-blocks that does not result in read disturb. Subsequently, the selected word line is raised to the appropriate read compare voltage so the selected memory cells can be sensed.
Public/Granted literature
- US20230386585A1 NON-VOLATILE MEMORY WITH ENGINEERED CHANNEL GRADIENT Public/Granted day:2023-11-30
Information query