Invention Grant
- Patent Title: Mitigation of duty-cycle distortion
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Application No.: US17404919Application Date: 2021-08-17
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Publication No.: US11881862B2Publication Date: 2024-01-23
- Inventor: Udayakiran Kumar Yallamaraju , Xia Li , Pankaj Deshmukh , Vajram Ghantasala , Bin Yang , Vishal Mishra , Bharatheesha Sudarshan Jagirdar , Arun Sundaresan Iyer , Amod Phadke , Vanamali Bhat
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM INCORPORATED
- Current Assignee: QUALCOMM INCORPORATED
- Current Assignee Address: US CA San Diego
- Agency: Loza & Loza, LLP
- Main IPC: H03K5/156
- IPC: H03K5/156 ; H03K5/134 ; H03K19/20 ; H03K5/00
Abstract:
A system includes a first park circuit having a signal input, an output, and a control input. The system also includes a first signal path having an input and an output, wherein the input of the first signal path is coupled to the output of the first park circuit. The system also includes a second park circuit having a signal input, an output, and a control input, wherein the signal input of the second park circuit is coupled to the output of the first signal path. The system further includes a second signal path having an input and an output, wherein the input of the second signal path is coupled to the output of the second park circuit.
Public/Granted literature
- US20230058318A1 MITIGATION OF DUTY-CYCLE DISTORTION Public/Granted day:2023-02-23
Information query
