Invention Grant
- Patent Title: Synchronization mechanisms for a multi-core processor using wait commands having either a blocking or a non-blocking state
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Application No.: US17469311Application Date: 2021-09-08
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Publication No.: US11892972B2Publication Date: 2024-02-06
- Inventor: Aaron Debattista , Jared Corey Smolens
- Applicant: Apical Limited , Arm Limited
- Applicant Address: GB Cambridge
- Assignee: Arm Limited
- Current Assignee: Arm Limited
- Current Assignee Address: GB Cambridge
- Agency: EIP US LLP
- Main IPC: G06F15/82
- IPC: G06F15/82 ; G06F9/48 ; G06F9/52 ; G06F8/41 ; G06F9/30 ; G06F9/38

Abstract:
Systems, apparatuses and methods suitable for optimizing synchronization mechanisms for multi-core processors are provided. The synchronizing mechanisms may be optimized by receiving a command stream which comprises a plurality of commands including one or more wait commands, wherein each wait command has an associated state and one or more associated conditions; sequentially processing each command in the command stream until a wait command is reached; checking the state associated with the wait command to be processed, wherein if said state is a blocking state, further processing of commands in the command stream is paused until each of said wait command's associated conditions are met, and wherein if said state is a non-blocking state, the next command in the command stream is retrieved and processed.
Public/Granted literature
- US20230077301A1 SYNCHRONIZATION MECHANISMS FOR A MULTI-CORE PROCESSOR Public/Granted day:2023-03-09
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