- 专利标题: Two-side staircase pre-charge in sub-block mode of three-tier non-volatile memory architecture
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申请号: US17724769申请日: 2022-04-20
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公开(公告)号: US11894072B2公开(公告)日: 2024-02-06
- 发明人: Jiacen Guo , Xiang Yang , Abhijith Prakash
- 申请人: SanDisk Technologies LLC
- 申请人地址: US TX Addison
- 专利权人: SANDISK TECHNOLOGIES LLC
- 当前专利权人: SANDISK TECHNOLOGIES LLC
- 当前专利权人地址: US TX Addison
- 代理机构: Dickinson Wright PLLC
- 主分类号: G11C16/08
- IPC分类号: G11C16/08 ; G11C16/34 ; G11C11/56 ; G11C16/10 ; G11C16/04
摘要:
A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and disposed in strings. A control means is coupled to the word lines and the strings and is configured to ramp a voltage applied to a selected one of the word lines from a verify voltage to a reduced voltage during a program-verify portion of a program operation. The control means successively ramps voltages applied to each of a plurality of neighboring ones of the word lines from a read pass voltage to the reduced voltage beginning with ones of the plurality of neighboring ones of the word lines immediately adjacent the selected one of the word lines and progressing to ones of the plurality of neighboring others of the word lines disposed increasingly remotely from the selected one of the word lines during the program-verify portion of the program operation.
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